Among semiconductor integrated circuits such as an LSI, there exists a multifunctional semiconductor integrated circuit (a multifunctional LSI) that realizes different functions according to a setting value (data) in a register. In recent years, improvements in the performance of the multifunctional LSI to get higher and more multiple functions have increased the amount of data that can be processed in the LSI. Also the number of registers to set up operation modes and various parameters to realize desired functions have increased. The setting of values to these registers is performed mainly by software or the firmware of a processor (for instance, a CPU or a DSP), which requires a considerable amount of time because of the increasing number of registers.
FIG. 7 is a block diagram showing a configuration example of a conventional multifunctional LSI. Note that as for a functional block, only four functional blocks from 73 to 76 are shown to simplify the explanation thereof in FIG. 7.
In FIG. 7, a processor 71 is structured including an instruction RAM (Random Access Memory) 72, and performs various functions such as microprocessing, register setting processing, and miscellaneous control processing. The instruction RAM 72 serves to store instruction codes and the like for commands to be performed by the processor 71.
A function block A73 is a functional unit which is composed of hardware, and includes a plurality of registers REGA. The function block A73 realizes a predetermined function according to values set in the registers REGA. Function blocks B74 to D76 are composed in a similar manner to the function block A73, and realize predetermined functions according to values set in a plurality of registers REGB to REGD which are included in respective function blocks.
The function blocks 73 to 76 are respectively connected to a processor bus PBUS of the processor 71, and the registers REGA to REGD which are included in the function blocks 73 to 76 are mapped in an external memory space of the processor 71. In the following explanation, the registers REGA are assumed to be mapped in a region of address values from F000 to F0FF in the external memory space, and the registers REGB, REGC, and REGD are assumed to be mapped in the regions of address values from F100 to F1FF, from F200 to 21FF, and from F300 to F3FF in the external memory space respectively.
FIG. 8 is a view showing an example of setting values to the registers from REGA to REGD in a multifunctional LSI shown in FIG. 7. It should be noted that a register from the registers REGA to REGD is supposed to be a 16-bit register.
For instance, in order to realize a first function (function 1: FUNC 1), “0001h” (h means it is expressed in a hexadecimal notation) is set to a register having an address of F000 of the function block A73, and “F000h” is set to a register having an address of F008, and so on. Similarly, “0001h” is set to an address of F100, “0011h” is set to an address of F101 of the function block B74, and so on, “0001h” is set to an address of F200, “FFFFh” is set to an address of F2F0 of the function block C75, and so on, and “0001h” is set to an address of F300, “4002h” is set to an address of F330 of the function block D76, and so on.
Also, for instance, in order to realize a second function (function 2: FUNC 2) which is different from the first function, “0002h” is set to an address of F000, “F0F0h” is set to an address of F008, and so on of the function block A73, and “0002h” is set to an address of F100, “0001h” is set to an address of F101, and so on of the function block B74, and “0002h” is set to an address of F200, “000Fh” is set to an address of F2F0, and so on of the function block C75, and “0002h” is set to an address of F300, “0002h” is set to an address of F330, and so on of the function block D76.
That is, in a multifunctional LSI as shown in FIG. 8, the number of registers to be set and their addresses differ according to the function to be realized, and even among the same registers, a setting value to be set differs according to a function. Therefore, in the instruction RAM 72 included in the processor 71, an instruction code of the processor 71 relating to register setting is written in each function as shown in FIG. 9, and the instructions to give access to registers are redundantly and repeatedly stored.
FIG. 9 is a view showing an example of an instruction code of the processor 71 relating to register setting stored in the instruction RAM 72. An instruction code 91 serves to realize the above-described first function (function 1). An address showing a register to be set is substituted to a variable (for instance, “MOV X=F000”), and then a setting value is written into the address which is substituted into the variable (for instance, “MOV (x++0), 0001h”). That is, a value is set to a register with two commands, and this procedure is repeated for the whole registers to be set in a similar manner. Note that instruction codes 92, 93, and so on to realize a second function (function 2), a third function (function 3), and so on are also stored similarly.
However, in a multifunctional LSI having many kinds of executable functions owing to increased functionality, there is a disadvantage in that the number of instruction codes stored in the instruction RAM 72 of the processor 71 dramatically increases and demands greater storage capacity to the instruction RAM 72. Another disadvantage is that the coding of instruction codes to be stored in the instruction RAM 72 becomes very difficult.
For instance, in a multifunctional LSI used in a cellular phone, the total number of registers in all function blocks is about 2000 pieces, and the types of functions (search of initial base stations after power-on, a phone conversation, intermittent reception and so on) numbers several hundred. Accordingly, assuming that values are set only to several hundred registers for one function, instructions numbering 104 or more (the number of commands is twice the number of instructions) are to be stored. Further, a change in a cellular phone system from a PDC (Personal Digital Cellular) system to a CDMA (Code Division Multiple Access) system increases the number of types of executable functions in a multifunctional LSI and increases further the number of function blocks as well as the number of registers associated with these functions.
As described above, the capacity of the instruction RAM 72 becomes large in the multifunctional LSI, and when regions occupied by the instruction RAM 72 becomes large in the processor 71, a logical portion in the processor 71 becomes small. Further, there is a disadvantage in that the ratio of register setting processing (writing into or reading from the register) occupied in processing of the processor 71 becomes large, which disturbs effective utilization of the processing capability (processing ability such as, for instance, calculation of field intensity in a case of a cellular phone) of the processor 71 in itself.
In addition, a method to prevent pressure of the instruction RAM 72 through stored instruction codes and to initialize plural registers is disclosed in a Patent Document 1.
Patent Document 1
Japanese Patent Application Laid-open No. Hei 8-153001